LD4 (multiple structures)
Load multiple 4-element structures to four registers
This instruction loads multiple 4-element structures
from memory and writes the result to the four SIMD&FP registers,
with de-interleaving.
For an example of de-interleaving, see LD3 (multiple structures).
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
It has encodings from 2 classes:
No offset
and
Post-index
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>]
constant integer t = UInt(Rt);
constant integer n = UInt(Rn);
constant integer m = integer UNKNOWN;
constant boolean wback = FALSE;
constant boolean nontemporal = FALSE;
constant boolean tagchecked = wback || n != 31;
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
1
1
LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <imm>
N
N
N
N
N
LD4 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>, <Vt4>.<T> }, [<Xn|SP>], <Xm>
constant integer t = UInt(Rt);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant boolean wback = TRUE;
constant boolean nontemporal = FALSE;
constant boolean tagchecked = wback || n != 31;
<Vt>
Is the name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field.
<T>
Is an arrangement specifier,
size
Q
<T>
00
0
8B
00
1
16B
01
0
4H
01
1
8H
10
0
2S
10
1
4S
11
0
RESERVED
11
1
2D
<Vt2>
Is the name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32.
<Vt3>
Is the name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32.
<Vt4>
Is the name of the fourth SIMD&FP register to be transferred, encoded as "Rt" plus 3 modulo 32.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<imm>
Is the post-index immediate offset,
<Xm>
Is the 64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.
constant integer datasize = 64 << UInt(Q);
constant integer esize = 8 << UInt(size);
constant integer elements = datasize DIV esize;
constant integer rpt = 1;
constant integer selem = 4;
// .1D format only permitted with LD1 & ST1
if size:Q == '110' && selem != 1 then UNDEFINED;
CheckFPAdvSIMDEnabled64();
bits(64) address;
bits(64) eaddr;
bits(64) offs;
bits(datasize) rval;
integer tt;
constant integer ebytes = esize DIV 8;
constant boolean privileged = PSTATE.EL != EL0;
constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked,
privileged);
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n, 64];
offs = Zeros(64);
for r = 0 to rpt-1
for e = 0 to elements-1
tt = (t + r) MOD 32;
for s = 0 to selem-1
rval = V[tt, datasize];
eaddr = AddressIncrement(address, offs, accdesc);
Elem[rval, e, esize] = Mem[eaddr, ebytes, accdesc];
V[tt, datasize] = rval;
offs = offs + ebytes;
tt = (tt + 1) MOD 32;
if wback then
if m != 31 then
offs = X[m, 64];
address = AddressAdd(address, offs, accdesc);
if n == 31 then
SP[] = address;
else
X[n, 64] = address;