LDAPR Load-acquire RCpc register This instruction derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release, created by having a Store-Release followed by a Load-AcquirePC instruction. The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer does not make the write of the Store-Release globally observed. This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. It has encodings from 2 classes: Post-index and No offset 1 x 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 LDAPR <Wt>, [<Xn|SP>], #4 1 LDAPR <Xt>, [<Xn|SP>], #8 constant integer t = UInt(Rt); constant integer n = UInt(Rn); boolean wback = TRUE; constant integer regsize = if size == '11' then 64 else 32; constant integer datasize = 8 << UInt(size); constant integer offset = 1 << UInt(size); constant boolean tagchecked = TRUE; boolean wb_unknown = FALSE; if n == t && n != 31 then constant Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP ExecuteAsNOP(); 1 x 1 1 1 0 0 0 1 0 1 (1) (1) (1) (1) (1) 1 1 0 0 0 0 0 LDAPR <Wt>, [<Xn|SP> {, #0}] 1 LDAPR <Xt>, [<Xn|SP> {, #0}] if !IsFeatureImplemented(FEAT_LRCPC) then UNDEFINED; constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant boolean wback = FALSE; constant integer offset = 0; constant boolean wb_unknown = FALSE; constant integer elsize = 8 << UInt(size); constant integer regsize = if elsize == 64 then 64 else 32; constant integer datasize = elsize; constant boolean tagchecked = n != 31; <Wt> Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <Xt> Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. bits(64) address; bits(datasize) data; constant integer dbytes = datasize DIV 8; constant AccessDescriptor accdesc = CreateAccDescLDAcqPC(tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; data = Mem[address, dbytes, accdesc]; X[t, regsize] = ZeroExtend(data, regsize); if wback then if wb_unknown then address = bits(64) UNKNOWN; else address = AddressAdd(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;