LDAPRH Load-acquire RCpc register halfword This instruction derives an address from a base register value, loads a halfword from the derived address in memory, zero-extends it and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release, created by having a Store-Release followed by a Load-AcquirePC instruction. The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer does not make the write of the Store-Release globally observed. This difference in memory ordering is not described in the pseudocode. For information about addressing modes, see Load/Store addressing modes. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. 0 1 1 1 1 0 0 0 1 0 1 (1) (1) (1) (1) (1) 1 1 0 0 0 0 LDAPRH <Wt>, [<Xn|SP> {, #0}] if !IsFeatureImplemented(FEAT_LRCPC) then UNDEFINED; constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant boolean tagchecked = n != 31; <Wt> Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. bits(64) address; bits(16) data; constant AccessDescriptor accdesc = CreateAccDescLDAcqPC(tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; data = Mem[address, 2, accdesc]; X[t, 32] = ZeroExtend(data, 32);