LDFF1W (scalar plus vector)
Gather load first-fault unsigned words to vector (vector index)
Gather load with first-faulting behavior of unsigned words to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
Green
True
True
SM_0_only
It has encodings from 6 classes:
32-bit scaled offset
,
32-bit unpacked scaled offset
,
32-bit unpacked unscaled offset
,
32-bit unscaled offset
,
64-bit scaled offset
and
64-bit unscaled offset
1
0
0
0
0
1
0
1
0
1
0
1
1
LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #2]
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED;
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 32;
constant integer msize = 32;
constant integer offs_size = 32;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = xs == '0';
constant integer scale = 2;
1
1
0
0
0
1
0
1
0
1
0
1
1
LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED;
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 32;
constant integer offs_size = 32;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = xs == '0';
constant integer scale = 2;
1
1
0
0
0
1
0
1
0
0
0
1
1
LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED;
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 32;
constant integer offs_size = 32;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = xs == '0';
constant integer scale = 0;
1
0
0
0
0
1
0
1
0
0
0
1
1
LDFF1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED;
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 32;
constant integer msize = 32;
constant integer offs_size = 32;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = xs == '0';
constant integer scale = 0;
1
1
0
0
0
1
0
1
0
1
1
1
1
1
LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED;
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 32;
constant integer offs_size = 64;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = TRUE;
constant integer scale = 2;
1
1
0
0
0
1
0
1
0
1
0
1
1
1
LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED;
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 32;
constant integer offs_size = 64;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = TRUE;
constant integer scale = 0;
<Zt>
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.
<Pg>
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Zm>
Is the name of the offset scalable vector register, encoded in the "Zm" field.
<mod>
Is the index extend and shift specifier,
CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant bits(PL) mask = P[g, PL];
bits(64) base;
bits(VL) offset;
bits(VL) result;
constant bits(VL) orig = Z[t, VL];
bits(msize) data;
constant integer mbytes = msize DIV 8;
boolean fault = FALSE;
boolean faulted = FALSE;
boolean unknown = FALSE;
constant boolean contiguous = FALSE;
constant boolean tagchecked = TRUE;
AccessDescriptor accdesc = CreateAccDescSVEFF(contiguous, tagchecked);
if !AnyActiveElement(mask, esize) then
if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
CheckSPAlignment();
else
if n == 31 then CheckSPAlignment();
base = if n == 31 then SP[] else X[n, 64];
offset = Z[m, VL];
assert accdesc.first;
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
constant integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned);
constant bits(64) addr = AddressAdd(base, off << scale, accdesc);
if accdesc.first then
// Mem[] will not return if a fault is detected for the first active element
data = Mem[addr, mbytes, accdesc];
accdesc.first = FALSE;
else
// MemNF[] will return fault=TRUE if access is not performed for any reason
(data, fault) = MemNF[addr, mbytes, accdesc];
else
(data, fault) = (Zeros(msize), FALSE);
// FFR elements set to FALSE following a suppressed access/fault
faulted = faulted || fault;
if faulted then
ElemFFR[e, esize] = '0';
// Value becomes CONSTRAINED UNPREDICTABLE after an FFR element is FALSE
unknown = unknown || ElemFFR[e, esize] == '0';
if unknown then
if !fault && ConstrainUnpredictableBool(Unpredictable_SVELDNFDATA) then
Elem[result, e, esize] = Extend(data, esize, unsigned);
elsif ConstrainUnpredictableBool(Unpredictable_SVELDNFZERO) then
Elem[result, e, esize] = Zeros(esize);
else // merge
Elem[result, e, esize] = Elem[orig, e, esize];
else
Elem[result, e, esize] = Extend(data, esize, unsigned);
Z[t, VL] = result;