LDGM Load tag multiple This instruction reads a naturally aligned block of N Allocation Tags, where the size of N is identified in GMID_EL1.BS, and writes the Allocation Tag read from address A to the destination register at 4*A<7:4>+3:4*A<7:4>. Bits of the destination register not written with an Allocation Tag are set to 0. This instruction is UNDEFINED at EL0. This instruction generates an Unchecked access. 1 1 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 LDGM <Xt>, [<Xn|SP>] if !IsFeatureImplemented(FEAT_MTE2) then UNDEFINED; constant integer t = UInt(Xt); constant integer n = UInt(Xn); <Xt> Is the 64-bit name of the general-purpose destination register, encoded in the "Xt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field. if PSTATE.EL == EL0 then UNDEFINED; bits(64) data = Zeros(64); bits(64) address; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; constant integer size = 4 * (2 ^ (UInt(GMID_EL1.BS))); address = Align(address, size); constant integer count = size >> LOG2_TAG_GRANULE; integer index = UInt(address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>); constant boolean devstoreunpred = FALSE; constant AccessDescriptor accdesc = CreateAccDescLDGSTG(MemOp_LOAD, devstoreunpred); for i = 0 to count-1 constant bits(4) tag = AArch64.MemTag[address, accdesc]; Elem[data, index, 4] = tag; address = AddressIncrement(address, TAG_GRANULE, accdesc); index = index + 1; X[t, 64] = data;