LDNF1H Contiguous load non-fault unsigned halfwords to vector (immediate index) Contiguous load with non-faulting behavior of unsigned halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled. Green True True SM_0_only It has encodings from 3 classes: 16-bit element , 32-bit element and 64-bit element 1 0 1 0 0 1 0 0 1 0 1 1 1 0 1 LDNF1H { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer g = UInt(Pg); constant integer esize = 16; constant integer msize = 16; constant boolean unsigned = TRUE; constant integer offset = SInt(imm4); 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 LDNF1H { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 16; constant boolean unsigned = TRUE; constant integer offset = SInt(imm4); 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 LDNF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant boolean unsigned = TRUE; constant integer offset = SInt(imm4); <Zt> Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <imm> Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field. CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; bits(64) addr; bits(VL) result; constant bits(VL) orig = Z[t, VL]; bits(msize) data; constant integer mbytes = msize DIV 8; boolean fault = FALSE; boolean faulted = FALSE; boolean unknown = FALSE; constant boolean contiguous = TRUE; constant boolean tagchecked = n != 31; constant AccessDescriptor accdesc = CreateAccDescSVENF(contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; addr = AddressAdd(base, offset * elements * mbytes, accdesc); for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then // MemNF[] will return fault=TRUE if access is not performed for any reason (data, fault) = MemNF[addr, mbytes, accdesc]; else (data, fault) = (Zeros(msize), FALSE); addr = AddressIncrement(addr, mbytes, accdesc); // FFR elements set to FALSE following a suppressed access/fault faulted = faulted || fault; if faulted then ElemFFR[e, esize] = '0'; // Value becomes CONSTRAINED UNPREDICTABLE after an FFR element is FALSE unknown = unknown || ElemFFR[e, esize] == '0'; if unknown then if !fault && ConstrainUnpredictableBool(Unpredictable_SVELDNFDATA) then Elem[result, e, esize] = Extend(data, esize, unsigned); elsif ConstrainUnpredictableBool(Unpredictable_SVELDNFZERO) then Elem[result, e, esize] = Zeros(esize); else // merge Elem[result, e, esize] = Elem[orig, e, esize]; else Elem[result, e, esize] = Extend(data, esize, unsigned); Z[t, VL] = result;