LDNP (SIMD&FP) Load pair of SIMD&FP registers, with non-temporal hint This instruction loads a pair of SIMD&FP registers from memory, issuing a hint to the memory system that the access is non-temporal. The address that is used for the load is calculated from a base register value and an optional immediate offset. For information about non-temporal pair instructions, see Load/Store SIMD and Floating-point non-temporal pair. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDNP (SIMD&FP). If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. 1 0 1 1 0 0 0 1 0 0 LDNP <St1>, <St2>, [<Xn|SP>{, #<imm>}] 0 1 LDNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] 1 0 LDNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] // Empty. <St1> Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. <St2> Is the 32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <imm> For the 32-bit variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4. <imm> For the 64-bit variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8. <imm> For the 128-bit variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16. <Dt1> Is the 64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. <Dt2> Is the 64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. <Qt1> Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field. <Qt2> Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field. constant integer t = UInt(Rt); constant integer t2 = UInt(Rt2); constant integer n = UInt(Rn); constant boolean nontemporal = TRUE; constant integer scale = 2 + (UInt(opc)); constant integer datasize = 8 << scale; constant bits(64) offset = LSL(SignExtend(imm7, 64), scale); constant boolean tagchecked = n != 31; boolean rt_unknown = FALSE; if t == t2 then constant Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // Result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP ExecuteAsNOP(); CheckFPEnabled64(); bits(64) address; bits(64) address2; constant integer dbytes = datasize DIV 8; constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked, privileged); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = AddressAdd(address, offset, accdesc); address2 = AddressIncrement(address, dbytes, accdesc); bits(datasize) data1 = Mem[address , dbytes, accdesc]; bits(datasize) data2 = Mem[address2, dbytes, accdesc]; if rt_unknown then data1 = bits(datasize) UNKNOWN; data2 = bits(datasize) UNKNOWN; V[t, datasize] = data1; V[t2, datasize] = data2;