LDPSW Load pair of registers signed word This instruction calculates an address from a base register value and an immediate offset, loads two 32-bit words from memory, sign-extends them, and writes them to two registers. For information about addressing modes, see Load/Store addressing modes. For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDPSW. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. It has encodings from 3 classes: Post-index , Pre-index and Signed offset 0 1 1 0 1 0 0 0 1 1 LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm> boolean wback = TRUE; constant boolean postindex = TRUE; 0 1 1 0 1 0 0 1 1 1 LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! boolean wback = TRUE; constant boolean postindex = FALSE; 0 1 1 0 1 0 0 1 0 1 LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] boolean wback = FALSE; constant boolean postindex = FALSE; <Xt1> Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. <Xt2> Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <imm> For the post-index and pre-index variant: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4. <imm> For the signed offset variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4. if L:opc<0> == '01' then UNDEFINED; constant integer t = UInt(Rt); constant integer t2 = UInt(Rt2); constant integer n = UInt(Rn); constant boolean nontemporal = FALSE; constant integer scale = 2 + UInt(opc<1>); constant integer datasize = 32; constant bits(64) offset = LSL(SignExtend(imm7, 64), scale); constant boolean tagchecked = wback || n != 31; boolean rt_unknown = FALSE; boolean wb_unknown = FALSE; if wback && (t == n || t2 == n) && n != 31 then constant Constraint c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // Writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // Writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP ExecuteAsNOP(); if t == t2 then constant Constraint c = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // Result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP ExecuteAsNOP(); bits(64) address; bits(64) address2; bits(datasize) data1; bits(datasize) data2; constant integer dbytes = datasize DIV 8; constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = AddressAdd(address, offset, accdesc); address2 = AddressIncrement(address, dbytes, accdesc); data1 = Mem[address , dbytes, accdesc]; data2 = Mem[address2, dbytes, accdesc]; if rt_unknown then data1 = bits(datasize) UNKNOWN; data2 = bits(datasize) UNKNOWN; X[t, 64] = SignExtend(data1, 64); X[t2, 64] = SignExtend(data2, 64); if wback then if wb_unknown then address = bits(64) UNKNOWN; elsif postindex then address = AddressAdd(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;