LDR (immediate, SIMD&FP) Load SIMD&FP register (immediate offset) This instruction loads an element from memory, and writes the result as a scalar to the SIMD&FP register. The address that is used for the load is calculated from a base register value, a signed immediate offset, and an optional offset that is a multiple of the element size. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. It has encodings from 3 classes: Post-index , Pre-index and Unsigned offset 1 1 1 1 0 0 x 1 0 0 1 0 0 0 LDR <Bt>, [<Xn|SP>], #<simm> 0 1 0 LDR <Ht>, [<Xn|SP>], #<simm> 1 0 0 LDR <St>, [<Xn|SP>], #<simm> 1 1 0 LDR <Dt>, [<Xn|SP>], #<simm> 0 0 1 LDR <Qt>, [<Xn|SP>], #<simm> if opc<1> == '1' && size != '00' then UNDEFINED; constant integer scale = if opc<1> == '1' then 4 else UInt(size); constant boolean wback = TRUE; constant boolean postindex = TRUE; constant bits(64) offset = SignExtend(imm9, 64); 1 1 1 1 0 0 x 1 0 1 1 0 0 0 LDR <Bt>, [<Xn|SP>, #<simm>]! 0 1 0 LDR <Ht>, [<Xn|SP>, #<simm>]! 1 0 0 LDR <St>, [<Xn|SP>, #<simm>]! 1 1 0 LDR <Dt>, [<Xn|SP>, #<simm>]! 0 0 1 LDR <Qt>, [<Xn|SP>, #<simm>]! if opc<1> == '1' && size != '00' then UNDEFINED; constant integer scale = if opc<1> == '1' then 4 else UInt(size); constant boolean wback = TRUE; constant boolean postindex = FALSE; constant bits(64) offset = SignExtend(imm9, 64); 1 1 1 1 0 1 x 1 0 0 0 LDR <Bt>, [<Xn|SP>{, #<pimm>}] 0 1 0 LDR <Ht>, [<Xn|SP>{, #<pimm>}] 1 0 0 LDR <St>, [<Xn|SP>{, #<pimm>}] 1 1 0 LDR <Dt>, [<Xn|SP>{, #<pimm>}] 0 0 1 LDR <Qt>, [<Xn|SP>{, #<pimm>}] if opc<1> == '1' && size != '00' then UNDEFINED; constant integer scale = if opc<1> == '1' then 4 else UInt(size); constant boolean wback = FALSE; constant boolean postindex = FALSE; constant bits(64) offset = LSL(ZeroExtend(imm12, 64), scale); <Bt> Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <simm> Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field. <Ht> Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. <St> Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. <Dt> Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. <Qt> Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. <pimm> For the 8-bit variant: is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field. <pimm> For the 16-bit variant: is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2. <pimm> For the 32-bit variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4. <pimm> For the 64-bit variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8. <pimm> For the 128-bit variant: is the optional positive immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0 and encoded in the "imm12" field as <pimm>/16. constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant integer datasize = 8 << scale; constant boolean nontemporal = FALSE; constant boolean tagchecked = wback || n != 31; CheckFPEnabled64(); bits(64) address; constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked, privileged); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = AddressAdd(address, offset, accdesc); V[t, datasize] = Mem[address, datasize DIV 8, accdesc]; if wback then if postindex then address = AddressAdd(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;