LDR (register)
Load register (register)
This instruction calculates an address from a base register
value and an offset register value, loads a word from memory, and
writes it to a register. The offset register value can optionally be
shifted and extended. For information about addressing modes, see
Load/Store addressing modes.
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
1
x
1
1
1
0
0
0
0
1
1
1
0
0
LDR <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
1
LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
if option<1> == '0' then UNDEFINED; // sub-word index
constant ExtendType extend_type = DecodeRegExtend(option);
constant integer scale = UInt(size);
constant integer shift = if S == '1' then scale else 0;
<Wt>
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Wm>
When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.
<Xm>
When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.
<extend>
Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted.
option
<extend>
010
UXTW
011
LSL
110
SXTW
111
SXTX
<amount>
For the 32-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
<amount>
For the 64-bit variant: is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
<Xt>
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
constant integer t = UInt(Rt);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer datasize = 8 << scale;
constant integer regsize = if datasize == 64 then 64 else 32;
constant boolean nontemporal = FALSE;
constant boolean tagchecked = TRUE;
constant bits(64) offset = ExtendReg(m, extend_type, shift, 64);
bits(64) address;
constant boolean privileged = PSTATE.EL != EL0;
constant AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged,
tagchecked);
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n, 64];
address = AddressAdd(address, offset, accdesc);
constant bits(datasize) data = Mem[address, datasize DIV 8, accdesc];
X[t, regsize] = ZeroExtend(data, regsize);