LDR (vector) Load vector register Load a vector register from a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current vector register size in bytes. This instruction is unpredicated. The load is performed as contiguous byte accesses, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes. Green True True 1 0 0 0 0 1 0 1 1 0 0 1 0 LDR <Zt>, [<Xn|SP>{, #<imm>, MUL VL}] if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer imm = SInt(imm9h:imm9l); <Zt> Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <imm> Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV 8; bits(64) base; constant integer offset = imm * elements; bits(VL) result; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = n != 31; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n, 64]; bits(64) addr = AddressAdd(base, offset, accdesc); constant boolean aligned = IsAligned(addr, 16); if !aligned && AlignmentEnforced() then AArch64.Abort(addr, AlignmentFault(accdesc)); for e = 0 to elements-1 Elem[result, e, 8] = AArch64.MemSingle[addr, 1, accdesc, aligned]; addr = AddressIncrement(addr, 1, accdesc); Z[t, VL] = result;