LDRSH (immediate) Load register signed halfword (immediate) This instruction loads a halfword from memory, sign-extends it to 32 bits or 64 bits, and writes the result to a register. The address that is used for the load is calculated from a base register and an immediate offset. For information about addressing modes, see Load/Store addressing modes. For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRSH (immediate). If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. It has encodings from 3 classes: Post-index , Pre-index and Unsigned offset 0 1 1 1 1 0 0 0 1 x 0 0 1 1 LDRSH <Wt>, [<Xn|SP>], #<simm> 0 LDRSH <Xt>, [<Xn|SP>], #<simm> boolean wback = TRUE; constant boolean postindex = TRUE; constant bits(64) offset = SignExtend(imm9, 64); 0 1 1 1 1 0 0 0 1 x 0 1 1 1 LDRSH <Wt>, [<Xn|SP>, #<simm>]! 0 LDRSH <Xt>, [<Xn|SP>, #<simm>]! boolean wback = TRUE; constant boolean postindex = FALSE; constant bits(64) offset = SignExtend(imm9, 64); 0 1 1 1 1 0 0 1 1 x 1 LDRSH <Wt>, [<Xn|SP>{, #<pimm>}] 0 LDRSH <Xt>, [<Xn|SP>{, #<pimm>}] boolean wback = FALSE; constant boolean postindex = FALSE; constant bits(64) offset = LSL(ZeroExtend(imm12, 64), 1); <Wt> Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <simm> Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field. <Xt> Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. <pimm> Is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2. constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant integer regsize = 64 >> UInt(opc<0>); constant boolean nontemporal = FALSE; constant boolean tagchecked = wback || n != 31; Constraint c; boolean wb_unknown = FALSE; if wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS wback = FALSE; // Writeback is suppressed when Constraint_UNKNOWN wb_unknown = TRUE; // Writeback is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP ExecuteAsNOP(); bits(64) address; constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = AddressAdd(address, offset, accdesc); constant bits(16) data = Mem[address, 2, accdesc]; X[t, regsize] = SignExtend(data, regsize); if wback then if wb_unknown then address = bits(64) UNKNOWN; elsif postindex then address = AddressAdd(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;