LDSETP, LDSETPA, LDSETPAL, LDSETPL Atomic bit set on quadword in memory This instruction atomically loads a 128-bit quadword from memory, performs a bitwise OR with the value held in a pair of registers on it, and stores the result back to memory. The value initially loaded from memory is returned in the same pair of registers. LDSETPA and LDSETPAL load from memory with acquire semantics. LDSETPL and LDSETPAL store to memory with release semantics. LDSETP has neither acquire nor release semantics. For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly CONSTRAINED UNPREDICTABLE behavior for A64 instructions. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 LDSETP <Xt1>, <Xt2>, [<Xn|SP>] 1 0 LDSETPA <Xt1>, <Xt2>, [<Xn|SP>] 1 1 LDSETPAL <Xt1>, <Xt2>, [<Xn|SP>] 0 1 LDSETPL <Xt1>, <Xt2>, [<Xn|SP>] if !IsFeatureImplemented(FEAT_LSE128) then UNDEFINED; if Rt == '11111' then UNDEFINED; if Rt2 == '11111' then UNDEFINED; constant integer t = UInt(Rt); constant integer t2 = UInt(Rt2); constant integer n = UInt(Rn); constant boolean acquire = A == '1'; constant boolean release = R == '1'; constant boolean tagchecked = n != 31; boolean rt_unknown = FALSE; if t == t2 then constant Constraint c = ConstrainUnpredictable(Unpredictable_LSE128OVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP ExecuteAsNOP(); <Xt1> Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. <Xt2> Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. bits(64) address; constant bits(64) value1 = X[t, 64]; constant bits(64) value2 = X[t2, 64]; bits(128) data; bits(128) store_value; constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_ORR, acquire, release, tagchecked, privileged); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; store_value = if BigEndian(accdesc.acctype) then value1:value2 else value2:value1; constant bits(128) comparevalue = bits(128) UNKNOWN; // Irrelevant when not executing CAS data = MemAtomic(address, comparevalue, store_value, accdesc); if rt_unknown then data = bits(128) UNKNOWN; if BigEndian(accdesc.acctype) then X[t, 64] = data<127:64>; X[t2, 64] = data<63:0>; else X[t, 64] = data<63:0>; X[t2, 64] = data<127:64>;