LSRV Logical shift right variable This instruction shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The remainder obtained by dividing the second source register by the data size defines the number of bits by which the first source register is right-shifted. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. This instruction is used by the alias LSR (register) Unconditionally The alias is always the preferred disassembly. 0 0 1 1 0 1 0 1 1 0 0 0 1 0 0 1 0 LSRV <Wd>, <Wn>, <Wm> 1 LSRV <Xd>, <Xn>, <Xm> constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer datasize = 32 << UInt(sf); constant ShiftType shift_type = DecodeShift(op2); <Wd> Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. <Wn> Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field. <Wm> Is the 32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field. <Xd> Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. <Xn> Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field. <Xm> Is the 64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field. Alias Conditions constant bits(datasize) operand2 = X[m, datasize]; X[d, datasize] = ShiftReg(n, shift_type, UInt(operand2) MOD datasize, datasize);