MLS (indexed) Multiply-subtract from accumulator (indexed) Multiply all integer elements within each 128-bit segment of the first source vector by the specified element in the corresponding second source vector segment. The products are then destructively subtracted from the corresponding elements of the addend and destination vector. The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment, encoded in 1 to 3 bits depending on the size of the element. This instruction is unpredicated. Green False True True It has encodings from 3 classes: 16-bit , 32-bit and 64-bit 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 MLS <Zda>.H, <Zn>.H, <Zm>.H[<imm>] if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 16; constant integer index = UInt(i3h:i3l); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda); 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 1 MLS <Zda>.S, <Zn>.S, <Zm>.S[<imm>] if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 32; constant integer index = UInt(i2); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda); 0 1 0 0 0 1 0 0 1 1 1 0 0 0 0 1 1 MLS <Zda>.D, <Zn>.D, <Zm>.D[<imm>] if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer index = UInt(i1); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda); <Zda> Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. <Zn> Is the name of the first source scalable vector register, encoded in the "Zn" field. <Zm> For the 16-bit and 32-bit variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field. <Zm> For the 64-bit variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field. <imm> For the 16-bit variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields. <imm> For the 32-bit variant: is the element index, in the range 0 to 3, encoded in the "i2" field. <imm> For the 64-bit variant: is the element index, in the range 0 to 1, encoded in the "i1" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant integer eltspersegment = 128 DIV esize; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; bits(VL) result = Z[da, VL]; for e = 0 to elements-1 constant integer segmentbase = e - (e MOD eltspersegment); constant integer s = segmentbase + index; constant integer element1 = UInt(Elem[operand1, e, esize]); constant integer element2 = UInt(Elem[operand2, s, esize]); constant bits(esize) product = (element1 * element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] - product; Z[da, VL] = result;