MOVA (vector to tile, four registers)
Move four vector registers to four ZA tile slices
The instruction operates on four consecutive horizontal or vertical slices within a named ZA tile of the specified element size.
The consecutive slice numbers within the tile are selected starting from the sum of the slice index register and immediate offset, modulo the number of such elements in a vector. The immediate offset is a multiple of 4 in the range 0 to the number of elements in a 128-bit vector segment minus 4.
This instruction is unpredicated.
Green
False
True
SM_1_only
This instruction is used by the alias
MOV (vector to tile, four registers)
Unconditionally
The alias is always the preferred disassembly.
It has encodings from 4 classes:
8-bit
,
16-bit
,
32-bit
and
64-bit
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
MOVA ZA0<HV>.B[<Ws>, <offs1>:<offs4>], { <Zn1>.B-<Zn4>.B }
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED;
constant integer s = UInt('011':Rs);
constant integer nreg = 4;
constant integer esize = 8;
constant integer n = UInt(Zn:'00');
constant integer d = 0;
constant integer offset = UInt(off2:'00');
constant boolean vertical = V == '1';
1
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
MOVA <ZAd><HV>.H[<Ws>, <offs1>:<offs4>], { <Zn1>.H-<Zn4>.H }
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED;
constant integer s = UInt('011':Rs);
constant integer nreg = 4;
constant integer esize = 16;
constant integer n = UInt(Zn:'00');
constant integer d = UInt(ZAd);
constant integer offset = UInt(o1:'00');
constant boolean vertical = V == '1';
1
1
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
MOVA <ZAd><HV>.S[<Ws>, <offs1>:<offs4>], { <Zn1>.S-<Zn4>.S }
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED;
constant integer s = UInt('011':Rs);
constant integer nreg = 4;
constant integer esize = 32;
constant integer n = UInt(Zn:'00');
constant integer d = UInt(ZAd);
constant integer offset = 0;
constant boolean vertical = V == '1';
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
MOVA <ZAd><HV>.D[<Ws>, <offs1>:<offs4>], { <Zn1>.D-<Zn4>.D }
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED;
if MaxImplementedSVL() < 256 then UNDEFINED;
constant integer s = UInt('011':Rs);
constant integer nreg = 4;
constant integer esize = 64;
constant integer n = UInt(Zn:'00');
constant integer d = UInt(ZAd);
constant integer offset = 0;
constant boolean vertical = V == '1';
<ZAd>
For the 16-bit variant: is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAd" field.
<ZAd>
For the 32-bit variant: is the name of the ZA tile ZA0-ZA3 to be accessed, encoded in the "ZAd" field.
<ZAd>
For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 to be accessed, encoded in the "ZAd" field.
<HV>
Is the horizontal or vertical slice indicator,
<Ws>
Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.
<offs1>
For the 8-bit variant: is the first slice index offset, encoded as "off2" field times 4.
<offs1>
For the 16-bit variant: is the first slice index offset, encoded as "o1" field times 4.
<offs1>
For the 32-bit and 64-bit variant: is the first slice index offset, with implicit value 0.
<offs4>
For the 8-bit variant: is the fourth slice index offset, encoded as "off2" field times 4 plus 3.
<offs4>
For the 16-bit variant: is the fourth slice index offset, encoded as "o1" field times 4 plus 3.
<offs4>
For the 32-bit and 64-bit variant: is the fourth slice index offset, with implicit value 3.
<Zn1>
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.
<Zn4>
Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.
CheckStreamingSVEAndZAEnabled();
constant integer VL = CurrentVL;
if nreg == 4 && esize == 64 && VL < 256 then UNDEFINED;
constant integer slices = VL DIV esize;
constant bits(32) index = X[s, 32];
constant integer slice = ((UInt(index) - (UInt(index) MOD nreg)) + offset) MOD slices;
for r = 0 to nreg-1
constant bits(VL) result = Z[n + r, VL];
ZAslice[d, esize, vertical, slice + r, VL] = result;