MOVA (vector to array, four registers) Move four vector registers to four ZA single-vector groups The instruction operates on four ZA single-vector groups. The single-vector group within each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo quarter the number of ZA array vectors. The vector group symbol VGx4 indicates that the instruction operates on four ZA single-vector groups. The preferred disassembly syntax uses a 64-bit element size, but an assembler should accept any element size if it is used consistently for all operands. The vector group symbol is preferred for disassembly, but optional in assembler source code. This instruction is unpredicated. Green False True SM_1_only This instruction is used by the alias MOV (vector to array, four registers) Unconditionally The alias is always the preferred disassembly. 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 MOVA ZA.D[<Wv>, <offs>{, VGx4}], { <Zn1>.D-<Zn4>.D } if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer offset = UInt(off3); constant integer n = UInt(Zn:'00'); constant integer nreg = 4; <Wv> Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. <offs> Is the vector select offset, in the range 0 to 7, encoded in the "off3" field. <Zn1> Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4. <Zn4> Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3. CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer vectors = VL DIV 8; constant integer vstride = vectors DIV nreg; constant bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; for r = 0 to nreg-1 constant bits(VL) result = Z[n + r, VL]; ZAvector[vec, VL] = result; vec = vec + vstride;