MVNI
Move inverted immediate (vector)
This instruction places the inverse of an immediate constant into every
vector element of the destination
SIMD&FP register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
If PSTATE.DIT is 1:
The execution time of this instruction is independent of:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
0
1
0
1
1
1
1
0
0
0
0
0
0
1
1
0
x
0
MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}
0
x
x
0
MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}
1
1
0
x
MVNI <Vd>.<T>, #<imm8>, MSL #<amount>
constant integer rd = UInt(Rd);
constant integer datasize = 64 << UInt(Q);
constant bits(64) imm64 = AdvSIMDExpandImm(op, cmode, a:b:c:d:e:f:g:h);
constant bits(datasize) imm = Replicate(imm64, datasize DIV 64);
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the 16-bit variant: is an arrangement specifier,
<T>
For the 32-bit variant: is an arrangement specifier,
<imm8>
Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".
<amount>
For the 16-bit shifted immediate variant: is the shift amount
cmode<1>
<amount>
0
0
1
8
defaulting to 0 if LSL is omitted.
<amount>
For the 32-bit shifted immediate variant: is the shift amount
cmode<2:1>
<amount>
00
0
01
8
10
16
11
24
defaulting to 0 if LSL is omitted.
<amount>
For the 32-bit shifting ones variant: is the shift amount
cmode<0>
<amount>
0
8
1
16
CheckFPAdvSIMDEnabled64();
V[rd, datasize] = NOT(imm);