NBSL Bitwise inverted select Selects bits from the first source vector where the corresponding bit in the third source vector is '1', and from the second source vector where the corresponding bit in the third source vector is '0'. The inverted result is placed destructively in the destination and first source vector. This instruction is unpredicated. Green False True True 0 0 0 0 0 1 0 0 1 1 1 0 0 1 1 1 1 NBSL <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer m = UInt(Zm); constant integer k = UInt(Zk); constant integer dn = UInt(Zdn); <Zdn> Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. <Zk> Is the name of the third source scalable vector register, encoded in the "Zk" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant bits(VL) operand1 = Z[dn, VL]; constant bits(VL) operand2 = Z[m, VL]; constant bits(VL) operand3 = Z[k, VL]; Z[dn, VL] = NOT((operand1 AND operand3) OR (operand2 AND NOT(operand3)));