NEG (vector) Negate (vector) This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. It has encodings from 2 classes: Scalar and Vector 0 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 0 NEG D<d>, D<n> if size != '11' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << UInt(size); constant integer datasize = esize; constant integer elements = 1; 0 1 0 1 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 NEG <Vd>.<T>, <Vn>.<T> if size:Q == '110' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; <d> Is the number of the SIMD&FP destination register, encoded in the "Rd" field. <n> Is the number of the SIMD&FP source register, encoded in the "Rn" field. <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, size Q <T> 00 0 8B 00 1 16B 01 0 4H 01 1 8H 10 0 2S 10 1 4S 11 0 RESERVED 11 1 2D <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = V[n, datasize]; bits(datasize) result; integer element; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); element = -element; Elem[result, e, esize] = element<esize-1:0>; V[d, datasize] = result;