ORR (vector, immediate)
Bitwise inclusive OR (vector, immediate)
This instruction reads each vector element from the destination
SIMD&FP register, performs a bitwise OR between each result
and an immediate constant, places the result into
a vector, and writes the vector to the
destination SIMD&FP register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
If PSTATE.DIT is 1:
The execution time of this instruction is independent of:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
0
0
0
1
1
1
1
0
0
0
0
0
x
x
x
1
0
1
1
0
ORR <Vd>.<T>, #<imm8>{, LSL #<amount>}
0
x
ORR <Vd>.<T>, #<imm8>{, LSL #<amount>}
constant integer rd = UInt(Rd);
constant integer datasize = 64 << UInt(Q);
constant bits(64) imm64 = AdvSIMDExpandImm(op, cmode, a:b:c:d:e:f:g:h);
constant bits(datasize) imm = Replicate(imm64, datasize DIV 64);
<Vd>
Is the name of the SIMD&FP register, encoded in the "Rd" field.
<T>
For the 16-bit variant: is an arrangement specifier,
<T>
For the 32-bit variant: is an arrangement specifier,
<imm8>
Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".
<amount>
For the 16-bit variant: is the shift amount
cmode<1>
<amount>
0
0
1
8
defaulting to 0 if LSL is omitted.
<amount>
For the 32-bit variant: is the shift amount
cmode<2:1>
<amount>
00
0
01
8
10
16
11
24
defaulting to 0 if LSL is omitted.
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand = V[rd, datasize];
V[rd, datasize] = operand OR imm;