ORR (immediate) Bitwise inclusive OR with immediate (unpredicated) Bitwise inclusive OR an immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. This instruction is unpredicated. Green False True True This instruction is used by the alias ORN (immediate) Never See below for details of when the alias is preferred. 0 0 0 0 0 1 0 1 0 0 0 0 0 0 ORR <Zdn>.<T>, <Zdn>.<T>, #<const> if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer dn = UInt(Zdn); bits(64) imm; (imm, -) = DecodeBitMasks(imm13<12>, imm13<5:0>, imm13<11:6>, TRUE, 64); <Zdn> Is the name of the source and destination scalable vector register, encoded in the "Zdn" field. <T> Is the size specifier, imm13<12> imm13<5:0> <T> 0 0xxxxx S 0 10xxxx H 0 110xxx B 0 1110xx B 0 11110x B 0 111110 RESERVED 0 111111 RESERVED 1 xxxxxx D <const> Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field. Alias Conditions CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV 64; constant bits(VL) operand = Z[dn, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(64) element1 = Elem[operand, e, 64]; Elem[result, e, 64] = element1 OR imm; Z[dn, VL] = result;