ORR (vectors, unpredicated) Bitwise inclusive OR vectors (unpredicated) Bitwise inclusive OR all elements of the second source vector with corresponding elements of the first source vector and place the first in the corresponding elements of the destination vector. This instruction is unpredicated. Green False True This instruction is used by the alias MOV (vector, unpredicated) Zn == Zm See below for details of when the alias is preferred. 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 ORR <Zd>.D, <Zn>.D, <Zm>.D if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <Zn> Is the name of the first source scalable vector register, encoded in the "Zn" field. <Zm> Is the name of the second source scalable vector register, encoded in the "Zm" field. Alias Conditions CheckSVEEnabled(); constant integer VL = CurrentVL; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; Z[d, VL] = operand1 OR operand2;