PRFH (scalar plus immediate) Contiguous prefetch halfwords (immediate index) Contiguous prefetch of halfword elements from the memory address generated by a 64-bit scalar base and immediate index in the range -32 to 31 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. The predicate may be used to suppress prefetches from unwanted addresses. Green True 1 0 0 0 0 1 0 1 1 1 0 0 1 0 PRFH <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 16; constant integer g = UInt(Pg); constant integer n = UInt(Rn); constant integer level = UInt(prfop<2:1>); constant boolean stream = (prfop<0> == '1'); constant PrefetchHint pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; constant integer scale = 1; constant integer offset = SInt(imm6); <prfop> Is the prefetch operation specifier, prfop <prfop> 0000 PLDL1KEEP 0001 PLDL1STRM 0010 PLDL2KEEP 0011 PLDL2STRM 0100 PLDL3KEEP 0101 PLDL3STRM x11x #uimm4 1000 PSTL1KEEP 1001 PSTL1STRM 1010 PSTL2KEEP 1011 PSTL2STRM 1100 PSTL3KEEP 1101 PSTL3STRM <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <imm> Is the optional signed immediate vector offset, in the range -32 to 31, defaulting to 0, encoded in the "imm6" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; bits(64) base; if AnyActiveElement(mask, esize) then base = if n == 31 then SP[] else X[n, 64]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant integer eoff = (offset * elements) + e; constant bits(64) addr = base + (eoff << scale); Hint_Prefetch(addr, pref_hint, level, stream);