RBIT (vector)
Reverse bit order (vector)
This instruction reads each vector element from the source SIMD&FP register,
reverses the bits of the element, places the results into a vector,
and writes the vector to the destination SIMD&FP register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
If PSTATE.DIT is 1:
The execution time of this instruction is independent of:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
0
1
0
1
1
1
0
0
1
1
0
0
0
0
0
0
1
0
1
1
0
RBIT <Vd>.<T>, <Vn>.<T>
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 8;
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV 8;
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
Is an arrangement specifier,
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand = V[n, datasize];
bits(datasize) result;
bits(esize) element;
bits(esize) rev;
for e = 0 to elements-1
element = Elem[operand, e, esize];
for i = 0 to esize-1
rev<(esize-1)-i> = element<i>;
Elem[result, e, esize] = rev;
V[d, datasize] = result;