RCWSSETP, RCWSSETPA, RCWSSETPL, RCWSSETPAL Read check write software atomic bit set on quadword in memory This instruction atomically loads a 128-bit quadword from memory, performs a bitwise OR with the value held in a pair of registers on it, and conditionally stores the result back to memory. Storing of the result back to memory is conditional on RCW Checks and RCWS Checks. The value initially loaded from memory is returned in the same pair of registers. This instruction updates the condition flags based on the result of the update of memory. RCWSSETPA and RCWSSETPAL load from memory with acquire semantics. RCWSSETPL and RCWSSETPAL store to memory with release semantics. RCWSSETP has neither acquire nor release semantics. For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly CONSTRAINED UNPREDICTABLE behavior for A64 instructions. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. 0 1 0 1 1 0 0 1 1 1 0 1 1 0 0 0 0 RCWSSETP <Xt1>, <Xt2>, [<Xn|SP>] 1 0 RCWSSETPA <Xt1>, <Xt2>, [<Xn|SP>] 1 1 RCWSSETPAL <Xt1>, <Xt2>, [<Xn|SP>] 0 1 RCWSSETPL <Xt1>, <Xt2>, [<Xn|SP>] if !IsFeatureImplemented(FEAT_D128) || !IsFeatureImplemented(FEAT_THE) then UNDEFINED; if Rt == '11111' then UNDEFINED; if Rt2 == '11111' then UNDEFINED; constant integer t = UInt(Rt); constant integer t2 = UInt(Rt2); constant integer n = UInt(Rn); constant boolean soft = TRUE; constant boolean acquire = A == '1'; constant boolean release = R == '1'; constant boolean tagchecked = n != 31; boolean rt_unknown = FALSE; if t == t2 then constant Constraint c = ConstrainUnpredictable(Unpredictable_LSE128OVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // result is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP ExecuteAsNOP(); <Xt1> Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field. <Xt2> Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. if !IsD128Enabled(PSTATE.EL) then UNDEFINED; bits(64) address; bits(64) value1; bits(64) value2; bits(128) newdata; bits(128) readdata; bits(4) nzcv; constant AccessDescriptor accdesc = CreateAccDescRCW(MemAtomicOp_ORR, soft, acquire, release, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; value1 = X[t, 64]; value2 = X[t2, 64]; newdata = if BigEndian(accdesc.acctype) then value1:value2 else value2:value1; constant bits(128) compdata = bits(128) UNKNOWN; // Irrelevant when not executing CAS (nzcv, readdata) = MemAtomicRCW(address, compdata, newdata, accdesc); PSTATE.<N,Z,C,V> = nzcv; if rt_unknown then readdata = bits(128) UNKNOWN; if BigEndian(accdesc.acctype) then X[t, 64] = readdata<127:64>; X[t2, 64] = readdata<63:0>; else X[t, 64] = readdata<63:0>; X[t2, 64] = readdata<127:64>;