REV16 (vector) Reverse elements in 16-bit halfwords (vector) This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 REV16 <Vd>.<T>, <Vn>.<T> constant integer csize = 64 >> UInt(o0:U); constant integer esize = 8 << UInt(size); if csize <= esize then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer datasize = 64 << UInt(Q); constant integer containers = datasize DIV csize; <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, size Q <T> 00 0 8B 00 1 16B 01 x RESERVED 1x x RESERVED <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = V[n, datasize]; bits(datasize) result; for c = 0 to containers-1 constant bits(csize) container = Elem[operand, c, csize]; Elem[result, c, csize] = Reverse(container, esize); V[d, datasize] = result;