SCVTF (scalar, fixed-point) Signed fixed-point convert to floating-point (scalar) This instruction converts the signed value in the 32-bit or 64-bit general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped. 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 1 SCVTF <Hd>, <Wn>, #<fbits> 1 1 1 SCVTF <Hd>, <Xn>, #<fbits> 0 0 0 SCVTF <Sd>, <Wn>, #<fbits> 1 0 0 SCVTF <Sd>, <Xn>, #<fbits> 0 0 1 SCVTF <Dd>, <Wn>, #<fbits> 1 0 1 SCVTF <Dd>, <Xn>, #<fbits> if ftype == '10' || (ftype == '11' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; if sf == '0' && scale<5> == '0' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer intsize = 32 << UInt(sf); constant integer decode_fltsize = 8 << UInt(ftype EOR '10'); constant integer fracbits = 64 - UInt(scale); constant boolean unsigned = FALSE; <Hd> Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Wn> Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field. <fbits> For the 32-bit to double-precision, 32-bit to half-precision and 32-bit to single-precision variant: is the number of bits after the binary point in the fixed-point source, in the range 1 to 32, encoded as 64 minus "scale". <fbits> For the 64-bit to double-precision, 64-bit to half-precision and 64-bit to single-precision variant: is the number of bits after the binary point in the fixed-point source, in the range 1 to 64, encoded as 64 minus "scale". <Xn> Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. CheckFPEnabled64(); constant boolean merge = IsMerging(FPCR); constant integer fltsize = if merge then 128 else decode_fltsize; bits(fltsize) fltval = if merge then V[d, fltsize] else Zeros(fltsize); constant bits(intsize) intval = X[n, intsize]; constant FPRounding rounding = FPRoundingMode(FPCR); Elem[fltval, 0, decode_fltsize] = FixedToFP(intval, fracbits, unsigned, FPCR, rounding, decode_fltsize); V[d, fltsize] = fltval;