SCVTF Multi-vector signed integer convert to floating-point Convert to single-precision from signed 32-bit integer, each element of the two or four source vectors, and place the results in the corresponding elements of the two or four destination vectors. This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors. This instruction is unpredicated. Green False SM_1_only It has encodings from 2 classes: Two registers and Four registers 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 SCVTF { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S } if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd:'0'); constant integer nreg = 2; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR); 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 SCVTF { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S } if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd:'00'); constant integer nreg = 4; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR); <Zd1> For the two registers variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2. <Zd1> For the four registers variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4. <Zd4> Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3. <Zd2> Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. <Zn1> For the two registers variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. <Zn1> For the four registers variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4. <Zn4> Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3. <Zn2> Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 32; array [0..3] of bits(VL) results; for r = 0 to nreg-1 constant bits(VL) operand = Z[n+r, VL]; for e = 0 to elements-1 constant bits(32) element = Elem[operand, e, 32]; Elem[results[r], e, 32] = FixedToFP(element, 0, unsigned, FPCR, rounding, 32); for r = 0 to nreg-1 Z[d+r, VL] = results[r];