SCVTF Signed integer convert to floating-point (predicated) Convert to floating-point from the signed integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified. If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element. Green True True True It has encodings from 7 classes: 16-bit to half-precision , 32-bit to half-precision , 32-bit to single-precision , 32-bit to double-precision , 64-bit to half-precision , 64-bit to single-precision and 64-bit to double-precision 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 SCVTF <Zd>.H, <Pg>/M, <Zn>.H if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 16; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 16; constant integer d_esize = 16; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR); 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 SCVTF <Zd>.H, <Pg>/M, <Zn>.S if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 32; constant integer d_esize = 16; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR); 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 SCVTF <Zd>.S, <Pg>/M, <Zn>.S if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 32; constant integer d_esize = 32; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR); 0 1 1 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 SCVTF <Zd>.D, <Pg>/M, <Zn>.S if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 32; constant integer d_esize = 64; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR); 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 SCVTF <Zd>.H, <Pg>/M, <Zn>.D if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 64; constant integer d_esize = 16; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR); 0 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 0 1 SCVTF <Zd>.S, <Pg>/M, <Zn>.D if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 64; constant integer d_esize = 32; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR); 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 0 1 0 1 SCVTF <Zd>.D, <Pg>/M, <Zn>.D if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 64; constant integer d_esize = 64; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR); <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(VL) result = Z[d, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(esize) element = Elem[operand, e, esize]; constant bits(d_esize) fpval = FixedToFP(element<s_esize-1:0>, 0, unsigned, FPCR, rounding, d_esize); Elem[result, e, esize] = ZeroExtend(fpval, esize); Z[d, VL] = result;