SETPTN, SETMTN, SETETN Memory set, unprivileged and non-temporal These instructions perform a memory set using the value in the bottom byte of the source register. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETPTN, then SETMTN, and then SETETN. SETPTN performs some preconditioning of the arguments suitable for using the SETMTN instruction, and performs an IMPLEMENTATION DEFINED amount of the memory set. SETMTN performs an IMPLEMENTATION DEFINED amount of the memory set. SETETN performs the last part of the memory set. The inclusion of IMPLEMENTATION DEFINED amounts of memory set allows some optimization of the size that can be performed. The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is IMPLEMENTATION DEFINED. Portable software should not assume that the choice of algorithm is constant. After execution of SETPTN, option A (which results in encoding PSTATE.C = 0): If Xn<63> == 1, the set size is saturated to 0x7FFFFFFFFFFFFFFF. Xd holds the original Xd + saturated Xn. Xn holds -1* saturated Xn + an IMPLEMENTATION DEFINED number of bytes set. PSTATE.{N,Z,V} are set to {0,0,0}. After execution of SETPTN, option B (which results in encoding PSTATE.C = 1): If Xn<63> == 1, the copy size is saturated to 0x7FFFFFFFFFFFFFFF. Xd holds the original Xd + an IMPLEMENTATION DEFINED number of bytes set. Xn holds the saturated Xn - an IMPLEMENTATION DEFINED number of bytes set. PSTATE.{N,Z,V} are set to {0,0,0}. For SETMTN, option A (encoded by PSTATE.C = 0), the format of the arguments is: Xn is treated as a signed 64-bit number. Xn holds -1* number of bytes remaining to be set in the memory set in total. Xd holds the lowest address that the set is made to -Xn. At the end of the instruction, the value of Xn is written back with -1* the number of bytes remaining to be set in the memory set in total. For SETMTN, option B (encoded by PSTATE.C = 1), the format of the arguments is: Xn holds the number of bytes remaining to be set in the memory set in total. Xd holds the lowest address that the set is made to. At the end of the instruction: the value of Xn is written back with the number of bytes remaining to be set in the memory set in total. the value of Xd is written back with the lowest address that has not been set. For SETETN, option A (encoded by PSTATE.C = 0), the format of the arguments is: Xn is treated as a signed 64-bit number. Xn holds -1* the number of bytes remaining to be set in the memory set in total. Xd holds the lowest address that the set is made to -Xn. At the end of the instruction, the value of Xn is written back with 0. For SETETN, option B (encoded by PSTATE.C = 1), the format of the arguments is: Xn holds the number of bytes remaining to be set in the memory set in total. Xd holds the lowest address that the set is made to. At the end of the instruction: the value of Xn is written back with 0. the value of Xd is written back with the lowest address that has not been set. Explicit Memory Write effects produced by the instruction behave as if the instruction was executed at EL0 if the Effective value of PSTATE.UAO is 0 and either: The instruction is executed at EL1. The instruction is executed at EL2 when the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. Otherwise, the Explicit Memory Write effects operate with the restrictions determined by the Exception level at which the instruction is executed. For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly Memory Copy and Memory Set SET*. 0 1 1 0 0 1 1 1 0 x x 1 1 0 1 0 0 SETPTN [<Xd>]!, <Xn>!, <Xs> 0 1 SETMTN [<Xd>]!, <Xn>!, <Xs> 1 0 SETETN [<Xd>]!, <Xn>!, <Xs> if !IsFeatureImplemented(FEAT_MOPS) || sz != '00' then UNDEFINED; SETParams memset; memset.d = UInt(Rd); memset.s = UInt(Rs); memset.n = UInt(Rn); constant bits(2) options = op2<1:0>; constant boolean nontemporal = options<1> == '1'; case op2<3:2> of when '00' memset.stage = MOPSStage_Prologue; when '01' memset.stage = MOPSStage_Main; when '10' memset.stage = MOPSStage_Epilogue; otherwise UNDEFINED; <Xd> For the prologue variant: is the 64-bit name of the general-purpose register that holds the destination address and is updated by the instruction, encoded in the "Rd" field. <Xd> For the epilogue and main variant: is the 64-bit name of the general-purpose register that holds an encoding of the destination address and for option B is updated by the instruction, encoded in the "Rd" field. <Xn> For the prologue variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field. <Xn> For the main variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set and is updated by the instruction, encoded in the "Rn" field. <Xn> For the epilogue variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set and is set to zero at the end of the instruction, encoded in the "Rn" field. <Xs> Is the 64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field. CheckMOPSEnabled(); CheckSETConstrainedUnpredictable(memset.n, memset.d, memset.s); constant bits(8) data = X[memset.s, 8]; MOPSBlockSize B; memset.is_setg = FALSE; memset.nzcv = PSTATE.<N,Z,C,V>; memset.toaddress = X[memset.d, 64]; if memset.stage == MOPSStage_Prologue then memset.setsize = UInt(X[memset.n, 64]); else memset.setsize = SInt(X[memset.n, 64]); memset.implements_option_a = SETOptionA(); constant boolean privileged = (if options<0> == '1' then AArch64.IsUnprivAccessPriv() else PSTATE.EL != EL0); constant AccessDescriptor accdesc = CreateAccDescMOPS(MemOp_STORE, privileged, nontemporal); if memset.stage == MOPSStage_Prologue then if memset.setsize > ArchMaxMOPSBlockSize then memset.setsize = ArchMaxMOPSBlockSize; if memset.implements_option_a then memset.nzcv = '0000'; memset.toaddress = memset.toaddress + memset.setsize; memset.setsize = 0 - memset.setsize; else memset.nzcv = '0010'; memset.stagesetsize = MemSetStageSize(memset); if memset.stage != MOPSStage_Prologue then CheckMemSetParams(memset, options); AddressDescriptor memaddrdesc; PhysMemRetStatus memstatus; integer memory_set; boolean fault = FALSE; if memset.implements_option_a then while memset.stagesetsize < 0 && !fault do // IMP DEF selection of the block size that is worked on. While many // implementations might make this constant, that is not assumed. B = SETSizeChoice(memset, 1); assert B <= -1 * memset.stagesetsize; (memory_set, memaddrdesc, memstatus) = MemSetBytes(memset.toaddress + memset.setsize, data, B, accdesc); if memory_set != B then fault = TRUE; else memset.setsize = memset.setsize + B; memset.stagesetsize = memset.stagesetsize + B; else while memset.stagesetsize > 0 && !fault do // IMP DEF selection of the block size that is worked on. While many // implementations might make this constant, that is not assumed. B = SETSizeChoice(memset, 1); assert B <= memset.stagesetsize; (memory_set, memaddrdesc, memstatus) = MemSetBytes(memset.toaddress, data, B, accdesc); if memory_set != B then fault = TRUE; else memset.toaddress = memset.toaddress + B; memset.setsize = memset.setsize - B; memset.stagesetsize = memset.stagesetsize - B; UpdateSetRegisters(memset, fault, memory_set); if fault then if IsFault(memaddrdesc) then AArch64.Abort(memaddrdesc.vaddress, memaddrdesc.fault); else constant boolean iswrite = TRUE; HandleExternalAbort(memstatus, iswrite, memaddrdesc, B, accdesc); if memset.stage == MOPSStage_Prologue then PSTATE.<N,Z,C,V> = memset.nzcv;