SHA512H2 SHA512 hash update part 2 This instruction takes the values from the three 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the sigma0 and majority functions of two iterations of the SHA512 computation. It returns this value to the destination SIMD&FP register. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. 1 1 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 SHA512H2 <Qd>, <Qn>, <Vm>.2D if !IsFeatureImplemented(FEAT_SHA512) then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); <Qd> Is the 128-bit name of the SIMD&FP source and destination register, encoded in the "Rd" field. <Qn> Is the 128-bit name of the second SIMD&FP source register, encoded in the "Rn" field. <Vm> Is the name of the third SIMD&FP source register, encoded in the "Rm" field. AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vtmp; bits(64) NSigma0; constant bits(128) x = V[n, 128]; constant bits(128) y = V[m, 128]; constant bits(128) w = V[d, 128]; NSigma0 = ROR(y<63:0>, 28) EOR ROR(y<63:0>, 34) EOR ROR(y<63:0>, 39); Vtmp<127:64> = (x<63:0> AND y<127:64>) EOR (x<63:0> AND y<63:0>) EOR (y<127:64> AND y<63:0>); Vtmp<127:64> = (Vtmp<127:64> + NSigma0 + w<127:64>); NSigma0 = ROR(Vtmp<127:64>, 28) EOR ROR(Vtmp<127:64>, 34) EOR ROR(Vtmp<127:64>, 39); Vtmp<63:0> = ((Vtmp<127:64> AND y<63:0>) EOR (Vtmp<127:64> AND y<127:64>) EOR (y<127:64> AND y<63:0>)); Vtmp<63:0> = (Vtmp<63:0> + NSigma0 + w<63:0>); V[d, 128] = Vtmp;