SHLL, SHLL2
Shift left long (by element size)
This instruction reads
each vector element in the lower or upper half of the
source SIMD&FP
register,
left shifts each result by the element size,
writes the final result to a vector,
and writes the
vector to the
destination SIMD&FP register.
The destination vector elements are twice
as long as the source vector elements.
The SHLL instruction extracts
vector elements from the lower half
of the source register. The SHLL2 instruction extracts
vector elements from the upper half
of the source register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
If PSTATE.DIT is 1:
The execution time of this instruction is independent of:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
0
1
0
1
1
1
0
1
0
0
0
0
1
0
0
1
1
1
0
SHLL{2} <Vd>.<Ta>, <Vn>.<Tb>, #<shift>
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
if size == '11' then UNDEFINED;
constant integer esize = 8 << UInt(size);
constant integer datasize = 64;
constant integer part = UInt(Q);
constant integer elements = datasize DIV esize;
constant integer shift = esize;
2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
Q
2
0
[absent]
1
[present]
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Ta>
Is an arrangement specifier,
size
<Ta>
00
8H
01
4S
10
2D
11
RESERVED
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<Tb>
Is an arrangement specifier,
size
Q
<Tb>
00
0
8B
00
1
16B
01
0
4H
01
1
8H
10
0
2S
10
1
4S
11
x
RESERVED
<shift>
Is the left shift amount, which must be equal to the source element width in bits,
size
<shift>
00
8
01
16
10
32
11
RESERVED
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand = Vpart[n, part, datasize];
bits(2*datasize) result;
integer element;
for e = 0 to elements-1
element = SInt(Elem[operand, e, esize]) << shift;
Elem[result, e, 2*esize] = element<2*esize-1:0>;
V[d, 2*datasize] = result;