SQCVTU (four registers)
Multi-vector signed saturating unsigned extract narrow
Saturate the signed integer value in each element of the four source vectors to unsigned integer value that is quarter the original source element width, and place the results in the quarter-width destination elements.
This instruction is unpredicated.
Green
False
SM_1_only
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
SQCVTU <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }
if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED;
constant integer esize = 8 << UInt(sz);
constant integer n = UInt(Zn:'00');
constant integer d = UInt(Zd);
<Zd>
Is the name of the destination scalable vector register, encoded in the "Zd" field.
<T>
Is the size specifier,
<Zn1>
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.
<Tb>
Is the size specifier,
<Zn4>
Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.
CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV (4 * esize);
bits(VL) result;
for r = 0 to 3
constant bits(VL) operand = Z[n+r, VL];
for e = 0 to elements-1
constant integer element = SInt(Elem[operand, e, 4 * esize]);
Elem[result, r*elements + e, esize] = UnsignedSat(element, esize);
Z[d, VL] = result;