SQDMLSLT (vectors)
Signed saturating doubling multiply-subtract long from accumulator (top)
Multiply then double the corresponding odd-numbered signed elements of the first and second source vectors. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1) to (2(N-1) )-1. Then destructively subtract from the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1) to (2(N-1) )-1. This instruction is unpredicated.
Green
False
True
0
1
0
0
0
1
0
0
0
0
1
1
0
1
1
SQDMLSLT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED;
if size == '00' then UNDEFINED;
constant integer esize = 8 << UInt(size);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer da = UInt(Zda);
constant integer sel1 = 1;
constant integer sel2 = 1;
<Zda>
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
<T>
Is the size specifier,
size
<T>
00
RESERVED
01
H
10
S
11
D
<Zn>
Is the name of the first source scalable vector register, encoded in the "Zn" field.
<Tb>
Is the size specifier,
size
<Tb>
00
RESERVED
01
B
10
H
11
S
<Zm>
Is the name of the second source scalable vector register, encoded in the "Zm" field.
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant bits(VL) operand1 = Z[n, VL];
constant bits(VL) operand2 = Z[m, VL];
bits(VL) result = Z[da, VL];
for e = 0 to elements-1
constant integer element1 = SInt(Elem[operand1, 2 * e + sel1, esize DIV 2]);
constant integer element2 = SInt(Elem[operand2, 2 * e + sel2, esize DIV 2]);
constant integer element3 = SInt(Elem[result, e, esize]);
constant integer product = SInt(SignedSat(2 * element1 * element2, esize));
Elem[result, e, esize] = SignedSat(element3 - product, esize);
Z[da, VL] = result;