SQDMLSLT (indexed)
Signed saturating doubling multiply-subtract long from accumulator (top, indexed)
Multiply then double the odd-numbered signed elements within each 128-bit segment of the first source vector and the specified signed element in the corresponding second source vector segment. Each intermediate value is saturated to the double-width N-bit value's signed integer range -2(N-1) to (2(N-1) )-1. Then destructively subtract from the overlapping double-width elements of the addend and destination vector. Each destination element is saturated to the double-width N-bit element's signed integer range -2(N-1) to (2(N-1) )-1.
The elements within the second source vector are specified using an immediate index which selects the same element position within each 128-bit vector segment. The index range is from 0 to one less than the number of elements per 128-bit segment, encoded in 2 or 3 bits depending on the size of the element.
Green
False
True
It has encodings from 2 classes:
32-bit
and
64-bit
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SQDMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED;
constant integer esize = 16;
constant integer index = UInt(i3h:i3l);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer da = UInt(Zda);
constant integer sel = 1;
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SQDMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED;
constant integer esize = 32;
constant integer index = UInt(i2h:i2l);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer da = UInt(Zda);
constant integer sel = 1;
<Zda>
Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
<Zn>
Is the name of the first source scalable vector register, encoded in the "Zn" field.
<Zm>
For the 32-bit variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.
<Zm>
For the 64-bit variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.
<imm>
For the 32-bit variant: is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.
<imm>
For the 64-bit variant: is the element index, in the range 0 to 3, encoded in the "i2h:i2l" fields.
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV (2 * esize);
constant integer eltspersegment = 128 DIV (2 * esize);
constant bits(VL) operand1 = Z[n, VL];
constant bits(VL) operand2 = Z[m, VL];
bits(VL) result = Z[da, VL];
for e = 0 to elements-1
constant integer s = e - (e MOD eltspersegment);
constant integer element1 = SInt(Elem[operand1, 2 * e + sel, esize]);
constant integer element2 = SInt(Elem[operand2, 2 * s + index, esize]);
constant integer element3 = SInt(Elem[result, e, 2*esize]);
constant integer product = SInt(SignedSat(2 * element1 * element2, 2*esize));
constant integer res = element3 - product;
Elem[result, e, 2*esize] = SignedSat(res, 2*esize);
Z[da, VL] = result;