SQDMULH (by element)
Signed saturating doubling multiply returning high half (by element)
This instruction multiplies each vector element in the first source SIMD&FP register
by the specified vector element of the
second source SIMD&FP register,
doubles the results, places the most significant half of the final results into a vector,
and writes the vector to the destination
SIMD&FP register.
The results are truncated.
For rounded results, see SQRDMULH.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
If PSTATE.DIT is 1:
The execution time of this instruction is independent of:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
The response of this instruction to asynchronous exceptions does not vary based on:
The values of the data supplied in any of its registers.
The values of the NZCV flags.
It has encodings from 2 classes:
Scalar
and
Vector
0
1
0
1
1
1
1
1
1
1
0
0
0
SQDMULH <V><d>, <V><n>, <Vm>.<Ts>[<index>]
constant integer idxdsize = 64 << UInt(H);
integer index;
bit Rmhi;
case size of
when '01' index = UInt(H:L:M); Rmhi = '0';
when '10' index = UInt(H:L); Rmhi = M;
otherwise UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rmhi:Rm);
constant integer esize = 8 << UInt(size);
constant integer datasize = esize;
constant integer elements = 1;
constant boolean round = FALSE;
0
0
0
1
1
1
1
1
1
0
0
0
SQDMULH <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]
constant integer idxdsize = 64 << UInt(H);
integer index;
bit Rmhi;
case size of
when '01' index = UInt(H:L:M); Rmhi = '0';
when '10' index = UInt(H:L); Rmhi = M;
otherwise UNDEFINED;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rmhi:Rm);
constant integer esize = 8 << UInt(size);
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;
constant boolean round = FALSE;
<V>
Is a width specifier,
size
<V>
00
RESERVED
01
H
10
S
11
RESERVED
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>
Is the number of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register,
size
<Vm>
00
RESERVED
01
UInt('0':Rm)
10
UInt(M:Rm)
11
RESERVED
Restricted to V0-V15 when element size <Ts> is H.
<Ts>
Is an element size specifier,
size
<Ts>
00
RESERVED
01
H
10
S
11
RESERVED
<index>
Is the element index,
size
<index>
00
RESERVED
01
UInt(H:L:M)
10
UInt(H:L)
11
RESERVED
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
Is an arrangement specifier,
size
Q
<T>
00
x
RESERVED
01
0
4H
01
1
8H
10
0
2S
10
1
4S
11
x
RESERVED
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand1 = V[n, datasize];
constant bits(idxdsize) operand2 = V[m, idxdsize];
bits(datasize) result;
integer element1;
integer element2;
integer product;
boolean sat;
element2 = SInt(Elem[operand2, index, esize]);
for e = 0 to elements-1
element1 = SInt(Elem[operand1, e, esize]);
product = 2 * element1 * element2;
product = RShr(product, esize, round);
// The following only saturates if element1 and element2 equal -(2^(esize-1))
(Elem[result, e, esize], sat) = SignedSatQ(product, esize);
if sat then FPSR.QC = '1';
V[d, datasize] = result;