SQRDMLSH (vector) Signed saturating rounding doubling multiply subtract returning high half (vector) This instruction multiplies the vector elements of the first source SIMD&FP register with the corresponding vector elements of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. It has encodings from 2 classes: Scalar and Vector 0 1 1 1 1 1 1 0 0 1 0 0 0 1 1 SQRDMLSH <V><d>, <V><n>, <V><m> if !IsFeatureImplemented(FEAT_RDM) then UNDEFINED; if size == '11' || size == '00' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer esize = 8 << UInt(size); constant integer datasize = esize; constant integer elements = 1; constant boolean rounding = TRUE; 0 1 0 1 1 1 0 0 1 0 0 0 1 1 SQRDMLSH <Vd>.<T>, <Vn>.<T>, <Vm>.<T> if !IsFeatureImplemented(FEAT_RDM) then UNDEFINED; if size == '11' || size == '00' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; constant boolean rounding = TRUE; <V> Is a width specifier, size <V> 00 RESERVED 01 H 10 S 11 RESERVED <d> Is the number of the SIMD&FP destination register, in the "Rd" field. <n> Is the number of the first SIMD&FP source register, encoded in the "Rn" field. <m> Is the number of the second SIMD&FP source register, encoded in the "Rm" field. <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, size Q <T> 00 x RESERVED 01 0 4H 01 1 8H 10 0 2S 10 1 4S 11 x RESERVED <Vn> Is the name of the first SIMD&FP source register, encoded in the "Rn" field. <Vm> Is the name of the second SIMD&FP source register, encoded in the "Rm" field. CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand1 = V[n, datasize]; constant bits(datasize) operand2 = V[m, datasize]; constant bits(datasize) operand3 = V[d, datasize]; bits(datasize) result; integer element1; integer element2; integer element3; integer accum; boolean sat; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); element3 = SInt(Elem[operand3, e, esize]); accum = (element3 << esize) - 2 * (element1 * element2); accum = RShr(accum, esize, rounding); (Elem[result, e, esize], sat) = SignedSatQ(accum, esize); if sat then FPSR.QC = '1'; V[d, datasize] = result;