SQSHLU
Signed saturating shift left unsigned by immediate
Shift left by immediate each active signed element of the source vector, and destructively place the results in the corresponding elements of the source vector. Each result element is saturated to the N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. Inactive elements in the destination vector register remain unmodified.
Green
True
True
True
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
SQSHLU <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED;
constant bits(4) tsize = tszh:tszl;
if tsize == '0000' then UNDEFINED;
constant integer esize = 8 << HighestSetBit(tsize);
constant integer g = UInt(Pg);
constant integer dn = UInt(Zdn);
constant integer shift = UInt(tsize:imm3) - esize;
<Zdn>
Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.
<T>
Is the size specifier,
tszh
tszl
<T>
00
00
RESERVED
00
01
B
00
1x
H
01
xx
S
1x
xx
D
<Pg>
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<const>
Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tszh:tszl:imm3".
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant bits(VL) operand1 = Z[dn, VL];
constant bits(PL) mask = P[g, PL];
bits(VL) result;
for e = 0 to elements-1
constant integer element1 = SInt(Elem[operand1, e, esize]);
if ActivePredicateElement(mask, e, esize) then
constant integer res = element1 << shift;
Elem[result, e, esize] = UnsignedSat(res, esize);
else
Elem[result, e, esize] = Elem[operand1, e, esize];
Z[dn, VL] = result;