SQXTN, SQXTN2 Signed saturating extract narrow This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values. If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set. The SQXTN instruction writes the vector to the lower half of the destination register and clears the upper half. The SQXTN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. It has encodings from 2 classes: Scalar and Vector 0 1 0 1 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 0 SQXTN <Vb><d>, <Va><n> if size == '11' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << UInt(size); constant integer datasize = esize; constant integer part = 0; constant integer elements = 1; constant boolean unsigned = FALSE; 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 0 SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta> if size == '11' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << UInt(size); constant integer datasize = 64; constant integer part = UInt(Q); constant integer elements = datasize DIV esize; constant boolean unsigned = FALSE; <Vb> Is the destination width specifier, size <Vb> 00 B 01 H 10 S 11 RESERVED <d> Is the number of the SIMD&FP destination register, encoded in the "Rd" field. <Va> Is the source width specifier, size <Va> 00 H 01 S 10 D 11 RESERVED <n> Is the number of the SIMD&FP source register, encoded in the "Rn" field. 2 Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is Q 2 0 [absent] 1 [present] <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <Tb> Is an arrangement specifier, size Q <Tb> 00 0 8B 00 1 16B 01 0 4H 01 1 8H 10 0 2S 10 1 4S 11 x RESERVED <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. <Ta> Is an arrangement specifier, size <Ta> 00 8H 01 4S 10 2D 11 RESERVED CheckFPAdvSIMDEnabled64(); constant bits(2*datasize) operand = V[n, 2*datasize]; bits(datasize) result; bits(2*esize) element; boolean sat; for e = 0 to elements-1 element = Elem[operand, e, 2*esize]; (Elem[result, e, esize], sat) = SatQ(SInt(element), esize, unsigned); if sat then FPSR.QC = '1'; Vpart[d, part, datasize] = result;