SQXTUNT Signed saturating unsigned extract narrow (top) Saturate the signed integer value in each source element to an unsigned integer value that is half the original source element width, and place the results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. Green False 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 SQXTUNT <Zd>.<T>, <Zn>.<Tb> if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant bits(3) tsize = tszh:tszl; if !(tsize IN {'001', '010', '100'}) then UNDEFINED; constant integer esize = 16 << HighestSetBitNZ(tsize); constant integer n = UInt(Zn); constant integer d = UInt(Zd); <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <T> Is the size specifier, tszh tszl <T> 0 00 RESERVED 0 01 B 0 10 H x 11 RESERVED 1 00 S 1 01 RESERVED 1 10 RESERVED <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. <Tb> Is the size specifier, tszh tszl <Tb> 0 00 RESERVED 0 01 H 0 10 S x 11 RESERVED 1 00 D 1 01 RESERVED 1 10 RESERVED CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[n, VL]; bits(VL) result = Z[d, VL]; constant integer halfesize = esize DIV 2; for e = 0 to elements-1 constant integer element1 = SInt(Elem[operand1, e, esize]); constant bits(halfesize) res = UnsignedSat(element1, halfesize); Elem[result, 2*e + 1, halfesize] = res; Z[d, VL] = result;