SRHADD Signed rounding halving add This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SHADD. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 0 1 1 1 0 1 0 0 0 1 0 1 SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> if size == '11' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, size Q <T> 00 0 8B 00 1 16B 01 0 4H 01 1 8H 10 0 2S 10 1 4S 11 x RESERVED <Vn> Is the name of the first SIMD&FP source register, encoded in the "Rn" field. <Vm> Is the name of the second SIMD&FP source register, encoded in the "Rm" field. CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand1 = V[n, datasize]; constant bits(datasize) operand2 = V[m, datasize]; bits(datasize) result; integer element1; integer element2; integer sum; for e = 0 to elements-1 element1 = SInt(Elem[operand1, e, esize]); element2 = SInt(Elem[operand2, e, esize]); sum = (element1 + element2 + 1) >> 1; Elem[result, e, esize] = sum<esize-1:0>; V[d, datasize] = result;