SRI Shift right and insert (immediate) This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. It has encodings from 2 classes: Scalar and Vector 0 1 1 1 1 1 1 1 0 1 x x x 0 1 0 0 0 1 SRI D<d>, D<n>, #<shift> if immh<3> != '1' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << 3; constant integer datasize = esize; constant integer elements = 1; constant integer shift = (esize * 2) - UInt(immh:immb); 0 1 0 1 1 1 1 0 != 0000 0 1 0 0 0 1 SRI <Vd>.<T>, <Vn>.<T>, #<shift> if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << HighestSetBitNZ(immh); constant integer datasize = 64 << UInt(Q); constant integer elements = datasize DIV esize; constant integer shift = (esize * 2) - UInt(immh:immb); <d> Is the number of the SIMD&FP destination register, in the "Rd" field. <n> Is the number of the first SIMD&FP source register, encoded in the "Rn" field. <shift> For the scalar variant: is the right shift amount, in the range 1 to 64, encoded as 128 - UInt("immh:immb"). <shift> For the vector variant: is the right shift amount, in the range 1 to the element width in bits, immh <shift> 0001 16 - UInt(immh:immb) 001x 32 - UInt(immh:immb) 01xx 64 - UInt(immh:immb) 1xxx 128 - UInt(immh:immb) <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <T> Is an arrangement specifier, immh Q <T> 0001 0 8B 0001 1 16B 001x 0 4H 001x 1 8H 01xx 0 2S 01xx 1 4S 1xxx 0 RESERVED 1xxx 1 2D <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = V[n, datasize]; constant bits(datasize) operand2 = V[d, datasize]; constant bits(esize) mask = LSR(Ones(esize), shift); bits(datasize) result; bits(esize) shifted; for e = 0 to elements-1 shifted = LSR(Elem[operand, e, esize], shift); Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted; V[d, datasize] = result;