SRI Shift right and insert (immediate) Shift each source vector element right by an immediate value, and insert the result into the corresponding vector element in the destination vector register, merging the shifted bits from each source element with existing bits in each destination vector element. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated. Green False True 0 1 0 0 0 1 0 1 0 1 1 1 1 0 0 SRI <Zd>.<T>, <Zn>.<T>, #<const> if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant bits(4) tsize = tszh:tszl; if tsize == '0000' then UNDEFINED; constant integer esize = 8 << HighestSetBit(tsize); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer shift = (2 * esize) - UInt(tsize:imm3); <Zd> Is the name of the destination scalable vector register, encoded in the "Zd" field. <T> Is the size specifier, tszh tszl <T> 00 00 RESERVED 00 01 B 00 1x H 01 xx S 1x xx D <Zn> Is the name of the source scalable vector register, encoded in the "Zn" field. <const> Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(VL) operand = Z[n, VL]; bits(VL) result = Z[d, VL]; for e = 0 to elements-1 constant bits(esize) element1 = Elem[result, e, esize]; constant bits(esize) element2 = Elem[operand, e, esize]; constant bits(esize) mask = LSR(Ones(esize), shift); constant bits(esize) shiftedval = LSR(element2, shift); Elem[result, e, esize] = (element1 AND (NOT mask)) OR shiftedval; Z[d, VL] = result;