SSHLL, SSHLL2 Signed shift left long (immediate) This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values. The SSHLL instruction extracts vector elements from the lower half of the source register. The SSHLL2 instruction extracts vector elements from the upper half of the source register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If PSTATE.DIT is 1: The execution time of this instruction is independent of: The values of the data supplied in any of its registers. The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on: The values of the data supplied in any of its registers. The values of the NZCV flags. This instruction is used by the alias SXTL, SXTL2 immb == '000' && BitCount(immh) == 1 See below for details of when the alias is preferred. 0 0 0 1 1 1 1 0 != 0000 1 0 1 0 0 1 SSHLL{2} <Vd>.<Ta>, <Vn>.<Tb>, #<shift> if immh == '0000' then SEE(asimdimm); if immh<3> == '1' then UNDEFINED; constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << HighestSetBitNZ(immh<2:0>); constant integer datasize = 64; constant integer part = UInt(Q); constant integer elements = datasize DIV esize; constant integer shift = UInt(immh:immb) - esize; constant boolean unsigned = FALSE; 2 Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is Q 2 0 [absent] 1 [present] <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <Ta> Is an arrangement specifier, immh <Ta> 0001 8H 001x 4S 01xx 2D 1xxx RESERVED <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. <Tb> Is an arrangement specifier, immh Q <Tb> 0001 0 8B 0001 1 16B 001x 0 4H 001x 1 8H 01xx 0 2S 01xx 1 4S 1xxx x RESERVED <shift> Is the left shift amount, in the range 0 to the source element width in bits minus 1, immh <shift> 0001 UInt(immh:immb) - 8 001x UInt(immh:immb) - 16 01xx UInt(immh:immb) - 32 1xxx RESERVED Alias Conditions CheckFPAdvSIMDEnabled64(); constant bits(datasize) operand = Vpart[n, part, datasize]; bits(datasize*2) result; integer element; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], unsigned) << shift; Elem[result, e, 2*esize] = element<2*esize-1:0>; V[d, datasize*2] = result;