ST1D (scalar plus scalar, consecutive registers) Contiguous store of doublewords from multiple consecutive vectors (scalar index) Contiguous store of doublewords from elements of two or four consecutive vector registers to the memory address generated by a 64-bit scalar base and scalar index which is added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory. Green True True True It has encodings from 2 classes: Two registers and Four registers 1 0 1 0 0 0 0 0 0 0 1 0 1 1 0 ST1D { <Zt1>.D-<Zt2>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then UNDEFINED; constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt('1':PNg); constant integer nreg = 2; constant integer t = UInt(Zt:'0'); constant integer esize = 64; 1 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 ST1D { <Zt1>.D-<Zt4>.D }, <PNg>, [<Xn|SP>, <Xm>, LSL #3] if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then UNDEFINED; constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt('1':PNg); constant integer nreg = 4; constant integer t = UInt(Zt:'00'); constant integer esize = 64; <Zt1> For the two registers variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 2. <Zt1> For the four registers variant: is the name of the first scalable vector register to be transferred, encoded as "Zt" times 4. <Zt4> Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" times 4 plus 3. <Zt2> Is the name of the second scalable vector register to be transferred, encoded as "Zt" times 2 plus 1. <PNg> Is the name of the governing scalable predicate register PN8-PN15, with predicate-as-counter encoding, encoded in the "PNg" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <Xm> Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. if IsFeatureImplemented(FEAT_SVE2p1) then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant integer mbytes = esize DIV 8; bits(64) offset; bits(64) base; bits(64) addr; bits(VL) src; constant bits(PL) pred = P[g, PL]; constant bits(PL * nreg) mask = CounterToPredicate(pred<15:0>, PL * nreg); constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant integer transfer = t; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; offset = X[m, 64]; addr = AddressAdd(base, UInt(offset) * mbytes, accdesc); for r = 0 to nreg-1 src = Z[transfer+r, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, r * elements + e, esize) then Mem[addr, mbytes, accdesc] = Elem[src, e, esize]; addr = AddressIncrement(addr, mbytes, accdesc);