ST1W (scalar plus immediate, single register)
Contiguous store words from vector (immediate index)
Contiguous store of words from elements of a vector register to the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements are not written to memory.
Green
True
True
True
SM_0_only
It has encodings from 2 classes:
SVE
and
SVE2
1
1
1
0
0
1
0
1
0
1
0
1
1
1
ST1W { <Zt>.<T> }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED;
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer g = UInt(Pg);
constant integer esize = 32 << UInt(sz);
constant integer msize = 32;
constant integer offset = SInt(imm4);
1
1
1
0
0
1
0
1
0
0
0
0
1
1
1
ST1W { <Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
if !IsFeatureImplemented(FEAT_SVE2p1) then UNDEFINED;
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer g = UInt(Pg);
constant integer esize = 128;
constant integer msize = 32;
constant integer offset = SInt(imm4);
<Zt>
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.
<T>
Is the size specifier,
<Pg>
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<imm>
Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.
if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
constant bits(PL) mask = P[g, PL];
bits(64) addr;
bits(VL) src;
constant integer mbytes = msize DIV 8;
constant boolean contiguous = TRUE;
constant boolean nontemporal = FALSE;
constant boolean tagchecked = n != 31;
constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous,
tagchecked);
if !AnyActiveElement(mask, esize) then
if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
CheckSPAlignment();
else
if n == 31 then CheckSPAlignment();
src = Z[t, VL];
base = if n == 31 then SP[] else X[n, 64];
addr = AddressAdd(base, offset * elements * mbytes, accdesc);
for e = 0 to elements-1
if ActivePredicateElement(mask, e, esize) then
Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;
addr = AddressIncrement(addr, mbytes, accdesc);