ST3D (scalar plus immediate) Contiguous store three-doubleword structures from three vectors (immediate index) Contiguous store three-doubleword structures, each from the same element number in three vector registers to the memory address generated by a 64-bit scalar base and an immediate index which is a multiple of 3 in the range -24 to 21 that is multiplied by the vector's in-memory size, irrespective of predication, Each predicate element applies to the same element number in each of the three vector registers, or equivalently to the three consecutive doublewords in memory which make up each structure. Inactive structures are not written to memory. Green True True True 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 ST3D { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}] if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer g = UInt(Pg); constant integer esize = 64; constant integer offset = SInt(imm4); constant integer nreg = 3; <Zt1> Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. <Zt2> Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. <Zt3> Is the name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32. <Pg> Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <imm> Is the optional signed immediate vector offset, a multiple of 3 in the range -24 to 21, defaulting to 0, encoded in the "imm4" field. CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; bits(64) addr; constant integer mbytes = esize DIV 8; array [0..2] of bits(VL) values; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = n != 31; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; addr = AddressAdd(base, offset * elements * nreg * mbytes, accdesc); for r = 0 to nreg-1 values[r] = Z[(t+r) MOD 32, VL]; for e = 0 to elements-1 for r = 0 to nreg-1 if ActivePredicateElement(mask, e, esize) then Mem[addr, mbytes, accdesc] = Elem[values[r], e, esize]; addr = AddressIncrement(addr, mbytes, accdesc);