STLLR Store LORelease register This instruction stores a 32-bit word or a 64-bit doubleword to a memory location, from a register. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. 1 x 0 0 1 0 0 0 1 0 0 (1) (1) (1) (1) (1) 0 (1) (1) (1) (1) (1) 0 STLLR <Wt>, [<Xn|SP>{, #0}] 1 STLLR <Xt>, [<Xn|SP>{, #0}] if !IsFeatureImplemented(FEAT_LOR) then UNDEFINED; constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant integer elsize = 8 << UInt(size); constant boolean tagchecked = n != 31; <Wt> Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <Xt> Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. bits(64) address; constant integer dbytes = elsize DIV 8; constant AccessDescriptor accdesc = CreateAccDescLOR(MemOp_STORE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; Mem[address, dbytes, accdesc] = X[t, elsize];