STLLRH Store LORelease register halfword This instruction stores a halfword from a 32-bit register to a memory location. The instruction also has memory ordering semantics as described in Load LOAcquire, Store LORelease. For information about addressing modes, see Load/Store addressing modes. If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored. 0 1 0 0 1 0 0 0 1 0 0 (1) (1) (1) (1) (1) 0 (1) (1) (1) (1) (1) STLLRH <Wt>, [<Xn|SP>{, #0}] if !IsFeatureImplemented(FEAT_LOR) then UNDEFINED; constant integer t = UInt(Rt); constant integer n = UInt(Rn); constant boolean tagchecked = n != 31; <Wt> Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. bits(64) address; constant AccessDescriptor accdesc = CreateAccDescLOR(MemOp_STORE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; Mem[address, 2, accdesc] = X[t, 16];